Output Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
Yes |
Recovered data streams as parallel data out of the receiver into the PLD source. |
Output port |
|
Yes |
Serial data output signal from the transmitter. |
Output port |
|
No |
Receiver output clock. |
Output port |
|
No |
Transmitter output clock. |
Output port |
|
No |
Receiver PLL is in locked mode with the reference clock indicator. |
Output port |
rx_freqlocked[] |
No |
Receiver PLL is in locked mode with the receiver data indicator. |
Output port |
rx_rlv[] |
No |
Channel violation of the specified
|
Output port |
rx_syncstatus[] |
No |
Output status from the pattern detector and word aligner indicator. |
Output port |
rx_patterndetect[] |
No |
Pattern detection indicator. |
Output port |
rx_ctrldetect[] |
No |
8B/10B decoder detection control code indicator. |
Output port |
rx_errdetect[] |
No |
8B/10B decoder detection error code indicator. |
Output port |
rx_disperr[] |
No |
8B/10B decoder detection disparity code indicator. |
Output port |
rx_runningdisp[] |
No |
Status signal. |
Output port |
rx_rmfifodatainserted[] |
No |
Rate matching FIFO data insertion status signal. |
Output port |
rx_rmfifodatadeleted[] |
No |
Rate matching FIFO data deletion status signal. |
Output port |
rx_bisterr[] |
No |
Error status signal for built-in self test (BIST). |
Output port |
rx_bistdone[] |
No |
Self test complete signal. |
Output port |
rx_a1a2sizeout[] |
No |
Signal after the |
Output port |
rx_signaldetect[] |
No |
Signal is at data input detection indicator. |
Output port |
pipestatus[] |
No |
3-bit |
Output port |
pipedatavalid[] |
No |
Valid data from the receiver indicator. |
Output port |
pipeelecidle[] |
No |
Electrical idle detection status signal. |
Output port |
pipephydonestatus[] |
No |
|
Output port |
rx_channelaligned[] |
No |
Deskew alignment status output indicator. |
Output port |
|
No |
CMU Phase-Locked Loop (PLL) Definition are locked to the respective input clock signal indicator. |
Output port |
|
No |
Source clock output to the PLD from the CMU clock divider. |
Output port |
rx_dataoutfull |
No |
64-bit output port from receiver during reconfiguration. |
Output port |
rx_recovclkout[] |
No |
Recovered clock output from the receiver. |
Output port Note:
This is an advanced option available only through the command line. |
rx_a1detect[] |
No |
A1 detect signal from the word aligner. |
Output port Note:
This is an advanced option available only through the command line. |
rx_a2detect[] |
No |
A2 detect signal from the word aligner. |
Output port Note:
This is an advanced option available only through the command line. |
rx_k1detect[] |
No |
K1 detect signal from the word aligner for the upper 10 bits. |
Output port Note:
This is an advanced option available only through the command line. |
|
No |
K2 detect signal from the word aligner for the upper 10 bits. |
Output port Note:
This is an advanced option available only through the command line. |
rx_rmfifoempty[] |
No |
Rate matching FIFO empty indicator. |
Output port Note:
This is an advanced option available only through the command line. |
rx_rmfifofull |
No |
Rate matching FIFO full indicator. |
Output port Note:
This is an advanced option available only through the command line. |
rx_rmfifoalmostempty[] |
No |
Rate matching FIFO almost empty indicator. |
Output port Note:
This is an advanced option available only through the command line. |
rx_rmfifoalmostfull[] |
No |
Rate matching FIFO almost full indicator. |
Output port Note:
This is an advanced option available only through the command line. |
rx_byteorderalignstatus[] |
No |
Signal from byte ordering block successful alignment indicator. |
Output port Note:
This is an advanced option available only through the command line. |
rx_phfifooverflow[] |
No |
Phase compensation FIFO overflow output signal. |
Output port Note:
This is an advanced option available only through the command line. |
rx_phfifounderflow[] |
No |
Phase compensation FIFO underflow output signal. |
Output port Note:
This is an advanced option available only through the command line. |
|
No |
|
Output port |
reconfig_fromgxb[] |
No |
Reconfiguration output to the PLD. |
Output port |
|
No |
Analog test bus output to the PLD. |
Output port |
|
No |
Phase compensation FIFO overflow indicator. |
Output port Note:
This is an advanced option available only through the command line. |
tx_phfifounderflow[] |
No |
Phase compensation FIFO underflow indicator. |
Output port Note:
This is an advanced option available only through the command line. |
cal_blk_calibrationstatus[] |
No |
5-bit 1-Ohm calibration result status signal. |
Output port Note:
This is an advanced option available only through the command line. |
rx_bitslipboundaryselectout[] |
No |
Bit slip boundary select output. |
Output port |
rx_revseriallpbkout[] |
No |
Reverse serial loopback output signal. |
Output port |
pll_locked_alt[] |
No |
Signal to indicate that the alternate CMU PLL is locked to the respective input clock signal. |
Output port |
tx_seriallpbkout[] |
No |
Serial loopback output signal. |
Output port |