Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
Yes |
Data input port to the receiver. |
Input port |
|
Yes |
Data input signal to the transmitter. |
Input port |
|
No |
Power down input for the receivers. |
Input port |
|
No |
quad Definition enable signal from the programmable logic device (PLD). |
The |
|
No |
Quad reset signal from the PLD. |
Input port
|
rx_invpolarity[] |
No |
Polarity inversion enable at the word aligner. |
Input port |
tx_invpolarity[] |
No |
Polarity inversion enable after the 8B/10B encoder. |
Input port |
rateswitch |
No |
Switch between PCI Express Gen1 and Gen2. |
The |
rx_revbyteorderwa[] |
No |
Byte order reversal enable from the word aligner. |
Input port |
rx_revbitorderwa[] |
No |
Bit order reversal enable from the word aligner. |
Input port |
rx_enabyteord[] |
No |
Dynamic byte ordering block enable. |
Input port |
rx_rmfifordena[] |
No |
Read operation enable for the rate matching FIFO. |
Input port |
rx_rmfifowrena[] |
No |
Write operation enable for the rate matching FIFO. |
Input port |
rx_rmfiforeset[] |
No |
Rate matching FIFO reset. |
Input port |
|
No |
Phase compensation FIFO reset. |
Input port |
tx_phfiforeset[] |
No |
Phase compensation FIFO reset. |
Input port |
tx_revparallellpbken[] |
No |
Dynamic reverse parallel feedback enable. |
Input port |
|
No |
Digital reset signal to reset the digital portion of the receiver. |
Input port |
|
No |
Digital reset signal to reset the digital portion of the transmitter. |
Input port |
|
No |
Analog reset signal to reset the analog portion of the receivers. |
Input port |
|
No |
Control signal that dynamically enables serial loopback. |
Input port |
|
No |
Receiver detect or loopback enable signal. |
Input port |
|
No |
PCI Express (PIPE) power down directive. |
Input port |
rx_coreclk[] |
No |
PLD clock network connection into the HSSI PCS receiver. |
Input port |
tx_coreclk[] |
No |
PLD clock network connection into the HSSI PCS transmitter. |
Input port |
|
Yes |
Clock input connection from the PLD source to the clock recovery unit (CRU) Definition. |
Input port |
|
Yes |
Clock connection for the CMU Phase-Locked Loop (PLL) Definition. |
|
|
No |
Receiver PLL lock to the received data. |
Input port |
|
No |
Receiver PLL lock to the reference clock. |
Input port |
|
No |
Control signal to drop one bit. |
Input port |
|
No |
Word alignment enable. |
Input port |
|
No |
Specifies A1A2 or A1A1A2A2 commas. |
Input port |
|
No |
Specifies the 8-bit control word. |
Input port |
|
No |
Forces the running disparity of the PIPE interface to negative. |
Input port |
|
No |
Forces the transmitter to send out an electrical idle signal. |
Input port |
|
No |
Transmitter receiver detection. |
A 125 MHz input clock signal must be provided
for the |
|
No |
Polarity inversion enable at the 8B/10B decoder input. |
Input port |
aeq_togxb[] |
No |
Receiver analog test bus select. Specifies which analog test bus output port reports status. |
Input port |
|
No |
Transmitter force disparity enable. |
Input port |
|
No |
Specifies whether the 8B/10B encoder codes the incoming word using positive or negative disparity. |
Input port |
|
No |
Calibration clock from the PLD to the calibration block. |
The |
|
No |
Power down signal from the PLD to the calibration block. |
Signal is active low. If |
reconfig_togxb[] |
No |
Specifies reconfigurable 3-bit input. |
Input port |
reconfig_clk[] |
No |
Reconfigurable clock input. |
Input port |
|
No |
Selects transmitter de-emphasis under PCI Express Gen2 speeds 1"™b0: -6 dB 1"™b1: -3.5 dB. |
Input port |
tx_pipedeemph[] |
No |
Controls the transmitter voltage swing level. |
Input port |
tx_pipeswing[] |
No |
Selects transmitter voltage levels, that is, voltage output differential (VOD) settings. |
Input port |
|
No |
Enables the consecutive identical digits (CID) mode in the pseudo-random binary sequence (PRBS) generator. |
Input port |
fixedclk_fast[] |
No |
Activates the soft-logic clock divider to
lower the |
Input port |
rx_seriallpbkin[] |
No |
Connects serial loopback input signal. |
Input port |
pll_inclk_rx_cruclk[] |
No |
PLL inclock bus for CMU PLL reconfiguration. |
Input port |
tx_revseriallpbkin[] |
No |
Connects reverse serial loopback input signal. |
Input port |
tx_bitslipboundaryselect[] |
No |
Indicates bit slip boundary select. |
Input port |