NAND Primitive

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Table 1.
Names:	Output Description:	Input Description:
`NAND2,NAND3,NAND4,NAND6,NAND8 ,NAND12`	`OUT` = logical `NAND` of inputs	`IN1, IN2, ...IN12`= 2, 3, 4, 6, 8, or 12 inputs

Note: In Verilog HDL, you must use the built-in nand gate primitive to implement the NAND logic function. Go to Using a Verilog HDL Gate Primitive for more information.