To perform a functional simulation with the QuestaSim GUI
- If you have not already done so, set up a project with the QuestaSim software.
- To map the design libraries to your work library:
- On the File menu, point to New and click Library (File menu). The Create a New Library dialog box appears.
- Type
lpm
in the Library Name box, type the name of the work library in the Library Maps to box, and then click OK. - Repeat steps 2a and 2b to map
altera_mf
to the work library.
- To compile the functional simulation libraries, Verilog HDL or
VHDL Design Files, and testbench files (if you are using a
testbench):Important: If your design contains the alt2gxb megafunction, refer to the alt2gxb Help topic for required settings information.
- On the Compile menu, click Compile.
- In the Library list of the Compile HDL Source Files dialog box, select the work library.
- In the File name list, type the directory path and file name of the appropriate simulation libraries.or
In the Files of Type list, select All Files (*.*), and in the Look in list select the Verilog HDL or VHDL Design File.
- Click Compile.Note: For VHDL designs that use the 220model.vhd library, turn on Use Explicit Declarations under Default Options in the Compile dialog box.
- Repeat steps 3b to 3d to compile the Verilog HDL or VHDL Design File.
- Repeat steps 3b to 3d to compile the testbench file(s).
- Click Done.
- To load the design:
- On the Simulate menu, click Simulate. The Simulate dialog box appears.
- In the Name list, click the + icon to expand the work directory.
- Select the top-level design file to simulate.
- Click Add.
- Click Load.
- Perform the functional simulation in the QuestaSim software.