To perform a timing simulation of a Verilog HDL design with the IES GUI
- If you have not already done so, perform Setting Up the Incisive Enterprise Simulator Working Environment.
-
Start the IES software by typing at a command prompt.
nclaunch
- On the File menu, click Set Design Directory.
- Browse to your design directory.
- Click Create cds.lib File. In the New cds.lib File dialog box, select the libraries to include and click Save.
-
Under Work Library, click New.
Note: Intel recommends using the IES (Verilog or VHDL) default library names when you create a library. You should name the IES software libraries as follows:
- When you run the IES software independently from the Quartus® Prime software, you should name your library work.
- When you run the IES software automatically from the Quartus® Prime software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate-level simulation.
-
Specify your new work library name; for example, type
work
. - Click OK.
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Repeat steps 8 and 9 for each functional simulation library; for example,
for other work library names, you could type
lpm
,altera_mf
,altera
. - In the Set Design Directory dialog box, click OK.
- In the Library Browser, right-click the files you want to compile, and then click NCVlog on the pop-up menu.
- In the Compile Verilog dialog box, you will see a list of all of the files you selected. Apply any wanted options, and then click OK.
- Repeat steps 12 and 13 to compile the Verilog Output File for the project and the appropriate library model files.
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To simulate the design, click Simulator and type
<work library>.<top-level entity name>
in the Design Unit text box. -
To direct the IES software to generate a Value Change Dump File (.vcd) Definition that you can then use to perform power analysis in the Quartus® Prime PowerPlay Power Analyzer:
-
In the file explorer pane, select the
<testbench or design instance name>
Tcl Script File (.tcl) Definition generated by the Quartus® Prime EDA Netlist Writer._dump_all_vcd_nodes.tcl
- On the File menu, click Source. The .tcl directs the IES software to monitor and write the output signals contained in the .tcl to a .vcd during simulation.
-
In the file explorer pane, select the