Perform a Gate-Level Simulation
- If you have not already done so, specify the settings to
generate netlist files.
- To verify that pre-existing libraries are not attached in the
Active-HDL software:
- On the View menu, click Library Manager. The Library Manager window appears.
- Browse to <Active-HDL installation directory>/vlib/altera_mf.
- If simulation libraries are present for your version of the Quartus® Primesoftware, you can skip to step 5. Otherwise you can download the appropriate version library files from the Aldec website or create them manually with steps 3 and 4.
- To create a workspace in the Active-HDL software and compile
simulation libraries:
- On the File menu, point to New and click Design. The New Design Wizard appears.
- Select Create an Empty Design and keep the Create New Workspace option selected.
- Click Next. The Property page appears. In the Property page, click Next.
- Type the name in the Design
name and Library
name fields, for example,
stratix_ver
. Select the location of your design in the Design folder field, and click Next. Intel recommends that you use same name for your design and the library. - Click Finish to complete the wizard.
- On the Design menu, click Add files to Design.
- Browse to Quartus® Prime< installation directory>/eda/sim_lib and add the necessary simulation model files. For example, compile thestratixiii_atoms.vmodel files into thestratixiii_verlibrary.
- On the Design menu, clickCompile Allto compile all the files and add them to the design library, for example,stratixiii_atoms.v.
- On the File menu, clickClose Workspace.
- You must map the created library in the Active-HDL
software. To register simulation libraries:
- On the View menu, clickLibrary Manager. The Library Manager window appears.
- On the Library menu, clickAttach Library.
- Locate the.libfile, for example,stratixiii.lib, from the design directory that you created in the previous steps and then clickOpen.
- To attach the simulation library as a global library inside your library manager and make it visible for any design in the Active-HDL software, turn onAttach as global library.
- To create a workspace in the Active-HDL software and
compile your testbench and design files into the work
library:
- On the File menu, point toNewand clickDesign. TheNew Design Wizardappears.
- SelectCreate an Empty Designand keep theCreate New Workspaceoption selected.
- ClickNext. ThePropertypage appears. In thePropertypage, clickNextto proceed to theDesign nameandLibrary namefields.
- Type
work
for the design name and select the location of your design. Intel recommends that you use same name for your design and the library. - ClickFinishto complete the wizard.
- On the Design menu, clickAdd files to Design.
- Browse to the Verilog HDL output file directory, for example,<project_directory>/simulation/activehdl, and add the Verilog Output File and Standard Delay Format Output File file.
- Browse to the testbench directory and add the testbench file.
- On the Design menu, clickCompile Allto compile the testbench and Verilog HDL output netlist files.
- To load a design in the Active-HDL software, in theDesign Browser, click theTop-level Selectionlist. Select the top-level module, which is your testbench with corresponding architecture.
- To initialize simulation in the Active-HDL software, on the Simulation menu, clickInitialize Simulation. This loads the simulation. TheDesign Browserautomatically switches to theStructuretab and displays the design tree.
- To perform the simulation in the Active-HDL
software:
- On the File menu, point toNewand clickWaveform.
- Drag signals of interest from theStructuretab of theDesign Browserto theWaveformwindow.
- On the Simulation menu, clickRun Until.
- In the pop-up window, specify how long you want your simulation to run, for example, 500 ns.