Commands for EDA Tools

Processing Menu Commands

You can use the Start Test Bench Template Writer command to generate Verilog Test Bench File (.vt) Definition and VHDL Test Bench File (.vht) Definition for simulation with other EDA simulation tools.

In the Quartus^® Prime Standard Edition, use the Start EDA Synthesis to run an EDA synthesis tool from within the Quartus^® Prime software.

You can use the Start EDA Netlist Writer to generate VHDL Output File (.vho) Definition SystemVerilog Output File (.svo) and Standard Delay Format Output File (.sdo) Definition for a design. You can compile a design and then specify different EDA tool settings and regenerate the netlist files without recompiling the design.

Tools Menu Commands

The RTL Simulation Tool and Gate Level Simulation Tool commStart EDA Synthesis Start EDA Synthesis ands allow you to run simulation tools automatically from within the Quartus^® Prime software after an initial compilation.