Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
No |
Data input to the shift register. |
Input port |
|
Yes |
Positive-edge-triggered clock. |
|
|
No |
Clock enable input. |
The shift options also use the enable input for the clock enable. For serial operation, enable must be high (1). For parallel load operation, load must be high (1) and enable must be high or unconnected. |
|
No |
Serial shift data input. |
At least one of the |
|
No |
Synchronous parallel load. High (1) equals load operation, and low (0) equals shift operation. |
Default is low (0) shift operation. For parallel load operation, load must be high (1), and enable must be high or unconnected. |
|
No |
Synchronous clear input. |
Clears the |
|
No |
Synchronous set input. |
Sets the |
|
No |
Asynchronous clear input. |
Asynchronously clears the |
|
No |
Asynchronous set input. |
Sets |