data[][]
|
Yes
|
Data input.
|
Input port, consisting of
LPM_SIZE buses, each LPM_WIDTH wide.
Two-dimensional bus ports are not supported in Verilog HDL.
|
sel[]
|
Yes
|
Selects one of the input buses.
|
Input port LPM_WIDTHS wide.
|
clock
|
No
|
Clock for pipelined usage.
|
The clock port provides pipelined
operation of the lpm_mux function. If an
LPM_PIPELINE value other than 0 (default value) is
specified, the clock port must be connected.
|
clken
|
No
|
Clock enable for pipelined usage.
|
If omitted, the default is 1.
|
aclr
|
No
|
Asynchronous clear for pipelined usage.
|
The pipeline initializes to an undefined
x
logic level. The aclr port can be used at any time to
reset the pipeline to all 0s, asynchronously to the
clock . However, the aclr port is used
only if the LPM_PIPELINE parameter is specified (with
a value other than 0) and the clock port is used.
|