Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
No |
Write enable input. |
The |
|
No |
Read enable input port. |
This port is available for StratixIII devices only. |
|
No |
Write enable input. |
The |
|
No |
Read enable input port. |
The |
|
No |
Data input port to the memory for port A. |
Input port |
|
No |
Data input port to the memory for port B. |
Input port |
|
Yes |
Address input to the memory for port A. |
Input port |
|
Yes |
Address input to the memory for port B. |
Input port |
|
Yes |
Clock input port for the RAM. |
|
|
No |
Clock input port for the RAM. |
|
|
No |
Clock enable for |
|
|
No |
Clock enable for |
|
|
No |
The first asynchronous clear input. |
|
|
No |
The second asynchronous clear input. |
|
|
No |
Byte enable input port. |
Input port |
|
No |
Byte enable input port. |
Input port |