Input Ports

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Port Name	Required	Description	Comments
`data`	Yes	Data input to the memory.	Input port `WIDTH` wide.
`rdaddress[]`	Yes	Read address input to the memory.	Input port `WIDTHAD` wide.
`rdaddressstall[]`	No	Read address stall input port. The `rdaddress` port must be registered.	For Stratix III and Stratix IV devices, the `USE_EAB` parameter value must be `"ON"` and the `RAM_BLOCK_TYPE` parameter value must be `"MLAB(LUTRAM)"`. For other device families, the value must be `"GND"`.
`wraddress[]`	Yes	Write address input to the memory.	Input port `WIDTHAD` wide.
`wraddressstall[]`	No	Write address stall input port. The `wraddress` port must be registered.	For Stratix III and Stratix IV devices, the `USE_EAB` parameter value must be `"ON"` and the `RAM_BLOCK_TYPE` parameter value must be `"MLAB(LUTRAM)"`. For other device families, the value must be `"GND"`.
byteena	No	Byte enable input port.	Input port`[WIDTH_BYTEENA - 1..0]` wide. For Stratix IV, the `USE_EAB` parameter value must be `"ON"`, the `RAM_BLOCK_TYPE` parameter value must be `"MLAB(LUTRAM)"`, and the `WIDTH` parameter must be a non-unary multiple of the `BYTE_SIZE` parameter. For other device families, the value must be `"VCC"`.
`wren`	Yes	Write enable input port.
`inclock`	No	Positive-edge-triggered input clock port.	Used for registered write ports, for example, `data`, `wraddress`, and `wren`. Can also be used for registered read ports, for example, `rdaddress` and `rden`.
`inclocken`	No	Clock enable port for `inclock`.
`rden`	No	Read enable input. Disables reading when low (0).
`outclock`	No	Positive-edge-triggered input clock port.	Used for the registered `q[]` port. Can also be used for registered read ports, for example, `rdaddress` and `rden`.
`outclocken`	No	Clock enable port for `outclock`.
`aclr`	No	Asynchronous clear input.	Affects registered inputs and outputs.