VHDL Component Declaration
The following VHDL component declaration is located in the VHDL Design File (.vhd) Definition ALTERA_MF_COMPONENTS.vhd in the <Quartus® Prime installation directory>\libraries\vhdl\altera_mf directory.
component altdpram
generic (
byte_size : natural := 0;
intended_device_family : string := "unused";
indata_aclr : string := "ON";
indata_reg : string := "INCLOCK";
lpm_file : string := "UNUSED";
maximum_depth : natural := 0;
numwords : natural := 0;
outdata_aclr : string := "ON";
outdata_reg : string := "UNREGISTERED";
ram_block_type : string := "AUTO";
rdaddress_aclr : string := "ON";
rdaddress_reg : string := "OUTCLOCK";
rdcontrol_aclr : string := "ON";
rdcontrol_reg : string := "OUTCLOCK";
read_during_write_mode_mixed_ports : string := "DONT_CARE";
use_eab : string := "ON";
width : natural;
width_byteena : natural := 1;
widthad : natural;
wraddress_aclr : string := "ON";
wraddress_reg : string := "INCLOCK";
wrcontrol_aclr : string := "ON";
wrcontrol_reg : string := "INCLOCK";
lpm_hint : string := "UNUSED";
lpm_type : string := "altdpram"
);
port(
aclr : in std_logic := '0';
byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
data : in std_logic_vector(width-1 downto 0) := (others => '1');
inclock : in std_logic := '1';
inclocken : in std_logic := '1';
outclock : in std_logic := '1';
outclocken : in std_logic := '1';
q : out std_logic_vector(width-1 downto 0);
rdaddress : in std_logic_vector(widthad-1 downto 0);
rdaddressstall : in std_logic := '0';
rden : in std_logic := '1';
wraddress : in std_logic_vector(widthad-1 downto 0);
wraddressstall : in std_logic := '0';
wren : in std_logic
);
end component;