Verilog HDL Example Instantiation

module test(in1,in2,oe,out,bidir,bidir_n);

    input in1;

    input in2;

    input oe;

    inout bidir;

    inout bidir_n;

    output out;

    wire tmp1;

 

    and(tmp1,in1,in2);

 

    ALT_IOBUF_DIFF inst(

                                .i(tmp1),

                                .oe(oe),

                                .o(out),

                                .io(bidir),

                                .iobar(bidir_n)

                            );

 

    defparam inst.io_standard = "LVDS";

    defparam inst.current_strength = "12mA";

endmodule