Verilog HDL Example Instantiation

module ddio_top (aset, combout, datain_h, datain_l, inclock, sclr, oe, outclock, bidir, bidir_n );

 

       input   aset;

       input sclr;

       input   datain_h;

       input    datain_l;

       input   inclock;

       input   oe;

       input   outclock;

       output   combout;

       inout bidir;

       inout bidir_n;

 

       wire tmp_oe;

       wire tmp_padio;

 

       //myddio_bidir is an instance of the altddio_bidir megafunction

       myddio_bidir sample_ddio (       .aset(aset),

                                        .combout(combout),

                                        .datain_h (datain_h),

                                        .datain_l(datain_l),

                                        .inclock(inclock),

                                        .oe(oe),

                                        .outclock(outclock),

                                        .padio(tmp_padio),

                                        .oe_out_port(tmp_oe),

                                        .sclr(sclr)

                                 );

 

ALT_BIDIR_DIFF my_bidir (.bidirin (tmp_padio), .oe (tmp_oe), .io (bidir), .iobar (bidir_n));

 

endmodule