Primitive/Port Interconnections

Not all primitives/ports may connect to all other primitives in a design file. The following lists show the possible interconnections for all primitives/ports except logic and WIRE primitives:

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Source

Destination

Primitive

OUTPUT/ OUT

BIDIR/ INOUT

TRI (1)

GLOBAL

LCELL

EXP

SOFT

Logic

INPUT/ IN (2)

INPUTorIN

Y

N

Y

Y

na

na

na

Y

Y

OUTPUTorOUT(3)

N

N

N

N

N

N

N

N

N

BIDIRorINOUT(3)

N

N

Y

N

na

na

na

Y

Y

TRI

Y

Y

(4)

na

(4)

(4)

(4)

(4)

(4)

OPNDRN

Y

Y

(4)

na

(4)

(4)

(4)

(4)

(4)

GLOBAL

na

N

Y

Y

na

na

na

na

na

LCELL

Y

N

Y

Y

na

na

na

Y

na

EXP

na

N

na

Y

na

na

na

Y

na

SOFT

Y

N

na

Y

na

na

na

Y

na

VCC

Y

N

Y

N

na

na

na

Y

N

GND

Y

N

Y

N

na

na

na

Y

N

Logic

Y

N

Y

Y

Y

Y

Y

Y

Y

Reg Out

Y

N

Y

Y

na

na

Y

Y

Y

CASCADE

na

na

na

N

na

na

na

Y

na
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Source

Destination
Primitive Register Port
 

CASCADE

OPNDRN

CLK

PRN

CLRN

INPUTorIN

na

Y

Y

Y

Y

OUTPUTorOUT (3)

na

N

N

N

N

BIDIRorINOUT (3)

na

Y

Y

Y

Y

TRI

na

(4)

(4)

(4)

(4)

OPNDRN

na

(4)

(4)

(4)

(4)

GLOBAL

na

na

Y

Y

Y

LCELL

na

Y

Y

Y

Y

EXP

na

na

na

na

na

SOFT

na

na

Y

Y

Y

VCC

na

Y

N

Y

Y

GND

na

Y

N

Y

Y

Logic

Y

Y

Y

Y

Y

Reg Out

na

Y

Y

Y

Y

CASCADE

na

na

na

na

na

Legend:

Y

Interconnection is legal.

N

Interconnection is illegal.

na

Interconnection is legal but not advisable or may implement logic inefficiently.

(1)

Includes both data and output enable inputs to TRI.

(2)

The INPUT or IN primitive/port can be fed only by device pins or higher levels in the hierarchy.

(3)

The OUTPUT (or OUT), and BIDIR (or INOUT) primitives/ports can drive out only to device pins or higher levels in the hierarchy.

(4)

These connections change to legal (Y) or not advisable (na) only if the output of the TRI or OPNDRN is also connected to a BIDIR/INOUT primitive/port.