About Simulating Designs

Simulation verifies design behavior before device programming. The Quartus^® Prime software supports RTL- and gate-level design simulation in various third-party simulators. Simulation involves setting up your simulator working environment, compiling simulation model libraries, running your simulator, and interpreting the results. The Quartus^® Prime software supports various custom and scripted simulation flows.

The Quartus^® Prime software supports both Verilog HDL and VHDL simulation of encrypted and unencrypted Intel FPGA IP cores. If your design includes Intel FPGA IP cores, you must compile any corresponding IP simulation models in your simulator with the rest of your design and testbench. The Quartus^® Prime software generates and copies the simulation models for IP cores to your project directory.

Note: Refer to Simulating Intel Designs in the Quartus^® Prime Handbook for more details.