An ASCII text file (with the extension .vt) that is generated by the Quartus® Prime Standard Edition software or with the Quartus® Prime Standard Edition Text Editor or any other standard text editor. A Verilog Test Bench File contains an instantiation of the top-level design entity for a design and simulation input vectors and simulation output vectors. You can use a Verilog Test Bench File for simulation of a design with other EDA tools.
You can create a Verilog Test Bench File from a vector source file in the Quartus® Prime Standard Edition software by choosing the Export command and exporting the file as a Verilog Test Bench File. You can also generate a template for a Verilog Test Bench File by compiling a design and choosing the Start Test Bench Template Writer command, which places the template in the /<project directory>/simulation/<EDA simulation tool> directory.