A group of I/O pins associated with a VREF pin that are grouped for the purpose of specifying voltage. Each VREF group is associated with a specific I/O bank, and all of the pins in a VREF group must use the same VREF voltage.
The format of a VREF group location is VREFGROUP_B<number>_N<number> , where B<number> represents the I/O bank number and N<number> represents the VREF index within the I/O bank. For example, the Quartus® Prime Standard Edition Settings File (.qsf) setting for a VREF group assignment is: set_location_assignment VREFGROUP_B3_N2 -to clock
For supported device(Arriaseries, Cyclone series, and Stratix series) family devices you can assign nodes and entities to VREF groups using the Assignment Editor, Pin Planner, and Chip Planner.