A VHDL Hardware Description Language file (with the extension .vht) that contains an instantiation of a design entity, usually the top-level design entity, and code to create simulation input vectors and to test the behavior of simulation output vectors. VHDL Test Bench Files are used with an EDA simulation tool to test the behavior of an HDL design entity.
You can create a VHDL Test Bench File from a vector source file in the Quartus® Prime Standard Edition software by exporting the file as a VHDL Test Bench File with the Export command. You can also generate a template for a VHDL Test Bench File by compiling a design and clicking the Start Test Bench Template Writer command, which places the template in the /<project directory>/simulation/<EDA simulation tool> directory by default.