The required timing performance for one or more elements in your design. This timing performance is typically referred to as "timing constraints" or "timing exceptions" for TimeQuest analysis. You can specify timing assignments and constraints to direct the Compiler to optimize fitting to meet your timing performance goals, and then view reports about the results of timing analysis.
Before running the TimeQuest analyzer, you must specify initial timing constraints that describe the clock characteristics, timing exceptions, and signal transition arrival, and signal transition required times. You can specify all timing constraints in the Synopsys Design Constraints (SDC) format using the GUI or command line interfaces. The Quartus® Prime Standard Edition Fitter optimizes the placement of logic in the device in order to meet your specified constraints.