In signal integrity analysis, signal margin is a measure of available noise tolerance. For a victim net driven to logic one (high), signal margin is the difference between quiet high (QH) and VIHmin. For a victim net driven to logic zero (low), signal margin is the difference between VILmax and quiet low (QL). A reasonable design goal for simultaneous switching noise (SSN) glitches is 50% of signal margin. This goal allows half of the signal margin to be taken up by the driving device, leaving the other half of the signal margin for system-level noise that may occur, for example, on the PCB, connectors, receiver package, and power supply, and for VREF tolerance.