A series of horizontal interconnect channels that span a width of 4, 8, or 24 Logic Array Block (LAB) columns. The horizontal interconnect routes signals to and from LABs, M512 and M4K memory blocks, M-RAMs, DSP blocks, multiplier blocks, and I/O elements.
A horizontal interconnect channel that spans a width of 4 LAB columns in MAXII devices. The horizontal interconnect routes signals to and from LABs and I/O elements.