QDRII SRAM memory devices transfer data on separate read and write ports, and on both the rising edge and falling edge of the clock signal, resulting in four data throughputs per clock cycle. The dedicated input and output ports eliminate bus contention issues. Unilateral buses also simplify board design and facilitate high-frequency designs.
QDRII SRAM devices use the HSTL I/O standard. QDRII SRAMs are supported in supported device(ArriaII, CycloneIII, CycloneIV, and Stratix series) families.