Programmable Power Technology Tiles Definition

Programmable Power Technology uses on-chip voltage regulators to enable StratixIII, StratixIV, and StratixV core logic to be programmed at the tile level for high-speed mode or low-power mode configuration. Tiles are defined as:

Tiles can be configured to operate in high-speed mode or low-power mode.

The Quartus® Prime Standard Editionsoftware automatically controls which tile should operate at high-speed mode or low-power mode based on the timing constraints specified for the design. The PowerPlay power optimization, Programmable Power Maximum High-Speed Fraction of Used LAB Tiles and Programmable Power Technology Optimization options available in the Advanced Settings (Fitter) dialog box control the high-speed mode or low-power mode tiles configuration along with other power optimization techniques implemented at the Fitter level.

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