A symbolic name that represents an input or output of a primitive or of a design file.
In Synopsys Design Constraints, a port is an input or output (such as a device pin) of a top-level module.
In AHDL, a port name in the Subdesign Section represents an input or output of the current file. This port name also appears in the Function Prototype for the function. When an instance of a primitive or lower-level design file is implemented with an Instance Declaration or an in-line logic function reference, its ports are used to connect it to other functions in the Text Design File (.tdf). After an instance is declared, its inputs and outputs are expressed as names in the format <instance name> . <port name> in the Logic Section. When an in-line logic function reference is used, either named port association or positional port association can be used to connect the function's ports to other functions in the Text Design File.
In a VHDL Output File (.vho), a port name in the Entity Declaration represents an input or output of the current file. When an instance of a primitive or lower-level design file is implemented with a Component Instantiation, its ports are connected to signals with Port Map Aspects.
In Verilog Output File (.vo), a port in a Module Declaration represents an input or output of the current file. When an instance of a lower-level design file is implemented with a Module Instantiation, its ports are connected by order or by name to the Module Declaration ports of the module being instantiated. When a primitive is implemented with a Module Instantiation, its ports can be connected only by order to other functions in the file. Verilog HDL gate primitives also contain ports (called "terminals"); when a gate primitive is implemented with a Gate Instantiation, its terminals are connected by order to the terminals of the gate being instantiated.
A port name in an AHDL Subdesign Section, VHDL Entity Declaration, or Verilog HDL Module Declaration or gate primitive is synonymous with a pin name in a Block Design File (.bdf). A port name that is appended to an instance name is synonymous with the full port name in an instance of a symbol in a Block Design File.
In the Block and Symbol Editors, a port is the location on the boundary of a symbol representing a signal in a Symbol File (.sym), a Block Symbol file (.bsf), a Block Design File, or a Graphic Design File (.gdf). A line (node) drawn in a schematic must connect to this port to be recognized by the Compiler as a connection between the logic in the current file and the logic in the primitive, megafunction, or macrofunction.
You can edit the port in the Ports tab (Symbol Properties dialog box).
Ports in Block and Symbol Editor files are synonymous with ports in AHDL Function Prototypes and VHDL Component Declarations. They are also synonymous with ports listed in the Subdesign Sections of lower-level Text Design Files; in Entity Declarations of lower-level VHDL Design Files; and in Module Declarations, Module Instantiations, and Gate Instantiations of Verilog Design Files (.v).