An unstable logic level on a signal. When performing a timing simulation, you can specify the time period that constitutes an oscillation and monitor the project for signals that do not stabilize within the defined period. When the performing a functional simulation, you can monitor the project for zero-time oscillation only. A zero-time oscillation may be caused by a combinational loop in the design or vector source file. The Simulator detects a combinational loop when an output signal does not achieve a stable output value at a particular fixed time. For example, if the Simulator reports a zero-time oscillation for the output signal a at time 10 ns, this means that at time 10 ns, the output signal a cannot achieve a stable output value, but instead, the value changes back and forth at that particular time. The detection of a combinational loop is more common during functional simulation due to the absence of timing delays. During a timing simulation that includes delays, the same signal may appear as a glitch across the same time period.