A net represents a wire carrying a signal that travels between different logical components of a design file.
For all languages and Quartus® Prime Standard Edition applications except Verilog HDL and Synopsys Design Constraints, nets are called "nodes." In the Block Editor files, nodes are represented as lines; in text files, they are symbolic names; in Waveform Editor files, they are waveforms.
In Verilog HDL, nets can be scalar or vector.
In Synopsys Design Constraints, a net is a connection between pins.