An Altera device family designed as a cost-effective solution for control path applications. The MAX II device architecture provides an instant-on, non-volatile architecture and includes a User Flash memory (UFM) block of 8K bits for non-volatile storage. MAX II devices feature low standby and dynamic power, MultiVolt core, hot socketing, and enhanced in-system programmability (ISP) capabilities. MAX II device densities range between 240 to 2,210 logic cells and include the EPM240, EPM570, EPM1270, and EPM2210 devices.
Each MAXII device contains a single UFM block, which is an 8192-bit version organized as a 512x16 memory.
The MAX II routing structure provides fast propagation delay and clock-to-output times. I/O standard support includes the 3.3-V PCI I/O standard, and LVCMOS and LVTTL I/O standards at 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels. The input buffer for each MAX II device I/O pin has an optional Schmitt Trigger Input I/O standard settings at 2.5-V and 3.3-V LVTTL. The Schmitt trigger allows input buffers to respond to slow input edge rates with a fast output edge rate.
MAX II devices have an internal linear voltage regulator which supports external supply voltages of 3.3 V or 2.5 V, regulating the supply down to the internal operating voltage of 1.8 V. MAX II Z devices accept only 1.8V as the external supply voltage.