LogicLock Region Definition

A LogicLock region is a type of placement constraint. You can define any arbitrary region of physical resources on the target device as a LogicLock region. When you assign nodes or entities to a LogicLock region, you direct the Compiler to place those nodes or entities inside the region during fitting. LogicLock regions are available for supported device(Cyclone IV, MAX II, and Stratix series) families.

A LogicLock region can have the following size and location settings:

The Quartus® Prime Standard Edition software determines an optimal size and location for auto-size and floating regions during compilation. If you are satisfied with the size or location chosen, you can back-annotate the size or location for reuse in subsequent compilations.

The Reserved option prevents the Fitter from placing nodes not assigned to the LogicLock region within the LogicLock region. To support team-based design, you can reserve areas of a device by creating a reserved LogicLock region without assigning nodes or entities to the LogicLock region.

LogicLock back-annotation allows you to back-annotate all nodes in a LogicLock region. Nodes back-annotated with LogicLock back-annotation are locked relative to the edges of the region. If you move a back-annotated region, its member nodes maintain their relative placement in the new location.

Note: To preserve synthesis and fitting results, Altera recommends that you use incremental compilation rather than LogicLock back-annotation. Back-annotation of LogicLock region nodes is available only for supported device (MAX series) families.

LogicLock regions can be nested hierarchically. If you move a parent region, child regions maintain their placement relative to their parent region.

LogicLock assignments can be exported in a Quartus® Prime Standard Edition Settings File (.qsf) for reuse in other designs.

You can create a LogicLock region without assigning nodes or entities to it. A LogicLock region is visible in the Chip Planner and the LogicLock Regions window until you delete it, regardless of whether any nodes are currently assigned to the LogicLock region.

For the design separation flow, the Quartus® Prime Standard Edition software provides three LogicLock region types:

An unsecured LogicLock region does not create a boundary of unused LABs, and does not have routing restrictions.

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