The smallest unit of logic located in a LAB of all Altera devices supported by the Quartus II software. A logic element is also generally known as a logic cell.
In supported device (Arria series, Cyclone series, and Stratix series) family devices, a logic element consists of a four-input LUT, a programmable register, and a carry chain. Supported device family logic elements also supports a dynamic single-bit addition or subtraction mode that is selectable by a LAB-wide control signal. Each logic element drives the local, row, column, carry chain, register chain, and direct link interconnects.
Each programmable register of a supported device(Arria series, Cyclone series, and Stratix series) family logic element can be configured for D, T, JK, or SR operation, or bypassed entirely for pure combinational logic. The register's clock, clear, clock enable, preset, asynchronous load, and asynchronous data control can be driven by general-purpose I/O pins or any internal logic. The register's clock and clear can also be driven by global signals.
You can assign a logic function to a specific logic element in supported device (Arria series, Cyclone series, and Stratix series) family devices. You can also assign a logic function to a Custom region to make sure the function is implemented in a logic element in that Custom region.
Logic elements have "numbers" of the following format for the following devices:
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Device Family |
Format for Logic Element "Numbers" |
Variable and Number Descriptions |
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|---|---|---|---|
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Arria series, Cyclone series, and Stratix series |
LC_X <number> _Y <number> _N <number> |
X <number> |
The column number that contains the LAB that contains the logic element. |
|
Y <number> |
The row number that contains the LAB that contains the logic element. |
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N <number> |
The logic element number ranging from 0 to 10. |
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