A generic term that refers to an assignable physical resource in the interior of an Altera device.
You can assign a node or entity to one of the following locations:
|
MAX II and MAX V |
Cyclone IV |
Stratix IV |
Stratix V |
|---|---|---|---|
|
An individual logic cell |
An individual logic cell |
An individual logic cell |
An individual logic cell |
|
An individual I/O pin |
An individual I/O pin |
An individual I/O pin |
An individual I/O pin |
|
A LAB |
A LAB |
A LAB or MLAB (StratixIV) |
A LAB or MLAB |
|
An M9K memory block |
An M-RAM or MLAB, an M512 or M4K, or M9k or M144K memory block |
M20K or MLAB memory block |
|
|
A PLL |
A DSP block |
A DSP block |
|
|
A Custom Region |
A Custom Region |
A DSP block multiplier |
A DSP block multiplier |
|
An I/O bank |
An I/O bank |
A PLL |
A PLL |
|
An edge |
An edge |
A SERDES receiver |
|
|
A multiplier block |
A SERDES transmitter |
||
|
A register |
A Custom Region |
A Custom Region |
|
|
An I/O bank |
An I/O bank |
||
|
An edge |
An edge |
||
|
A GXB receiver channel (Cyclone IV GX) |
A register or a GXB receiver channel (Stratix IV) |
||
|
A GXB receiver (Cyclone IV GX) |
A GXB receiver (Stratix IV) |
||
You can make assignments to locations using the Assignment Editor, the Timing Closure Floorplan, or the Chip Planner. You can also make assignments to regions or custom regions, which are multicell locations, in the Timing Closure Floorplan Regions window. When you assign a logic function to a general location such as a LAB, row, or column, the Compiler can choose the best logic cell or embedded cell within the LAB, row, or column to use to implement the logic. When creating location assignments for M512 memory blocks, M4K memory blocks, M-RAMs, M9K, M144K, M20K, or MLAB, you should only use legal node names, and not the names found in the Fitter RAM Summary section of the Report window.