A group of I/O pins that are grouped for the purpose of specifying I/O standards. Each I/O pin of the device is associated with a specific I/O bank, and the I/O banks are numbered. Pins that belong to the same I/O bank must use the same VCCIO signal and the same VREF signal if the I/O standard they operate at requires a VREF.
You can assign an I/O standard to the pins in an I/O bank by using the Assignment Editor or Pin Planner, and you can view the arrangement of I/O banks in the Chip Planner or Timing Closure Floorplan. Only one VREF voltage level can be assigned to the I/O pins in any given I/O bank.
You can assign nodes and entities to I/O banks using the Assignment Editor, Chip Planner, Pin Planner and the Timing Closure Floorplan for supported device(Arria series, Cyclone series, MAX II, MAX V, and Stratix series) families.