A feature available in Stratix V devices that employs a phase-locked loop (PLL). You can configure the fractional PLL (fPLL) as a single PLL or as two PLLs that you can use for independent applications. When configured individually, the fPLL is configured in conventional integer mode, which is equivalent to a general purpose PLL (GPLL). When configured as two PLLs, the output counters are shared between both PLLs in the block, and the fPLL is configured in enhanced fractional mode with third-order delta-sigma modulation.
You can use fPLLs to reduce the number of oscillators required on the board, as well as reduce clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source. In addition, you can use fPLLs for clock network delay compensation, zero-delay buffering, and transmit clocking for transceivers.