Dedicated circuitry on supported device (Arria series, Stratix IV, Stratix V) families devices used for dynamic phase alignment (DPA). The dynamic phase aligner enhances the SERDES receiver by reducing the need to match clock and data path delays in order to have the same phase during deserialization. The data is sampled by continuously selecting the optimal clock phase from the multiple phases provided by the fast PLL. The DPA circuit can capture the correct serial data bits on every channel, regardless of the channel-to-channel skew.