The DQS I/O pin in supported device (Arria series and Stratix series) family devices is the strobe pin in a bidirectional bus. Data pins in the bus are labeled DQ and the strobe pin is labeled DQS. You can optionally use the nDQS complement strobe pin, which allows support for DDR II SDRAM, QDR II SRAM, and RLDRAM II.
The DQS I/O pin in Cyclone series family devices is a strobe pin that can also be used as a normal data pin. Data is latched using double data rate (DDR) circuitry in a Cyclone series device. Data pins in the DDR circuitry are labeled DQ and the strobe pin is labeled DQS.
RAM that use DDR are designed to transfer two data words per clock cycle, using both the positive and the negative edge of the clock. With each word of data, a data-strobe (clock) is transferred for synchronization. Typically, for each 8 bits of data (DQ[7..0]), a single DQS signal is needed.
In input mode (reading from the RAM), the device receives the DQ signals edge-aligned with the DQS strobe. To maximize setup and hold constraints, the clock (DQS) is delayed internally using a delay locked loop that shifts the data 90 degrees with respect to the system clock. The data is latched using the DDIO circuitry.
In output mode (writing to the RAM), the device sends the DQ signals center-aligned (90 degrees) out of phase with the DQS signal. This is done by generating a clock using the DDIO circuitry in the PLD and shifting the output clock of the data by 90 degrees using PLLs.