design unit Definition

A design entity that can be used together with gate and flipflop primitives and/or megafunctions in Quartus^® Prime Standard Edition design files.

Entities include the following:

• user AHDL macrofunctions
• Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) entity-architecture design units
• Verilog HDL modules
• EDIF cells inside an EDIF design
• user schematic (or block diagram) macrofunctions
• library of parameterized modules (LPM) functions
• megafunctions