A feature available in supported device (Arria series, Cyclone series, and Stratix series) families that transfers data on both the rising edge and falling edge of the clock signal, and therefore doubles the memory bandwidth by transferring data twice per cycle. Addresses and control signals are registered at every positive clock edge.
You can take advantage of DDR with the altddio_in, altddio_out, and altddio_bidir megafunctions.