A series of vertical interconnect channels that span a height of 4, 8, or 16 Logic Array Block (LAB) rows. The vertical interconnect routes signals to and from LABs, M512 and M4K memory blocks, M-RAMs, DSP blocks, and I/O elements.
A vertical interconnect channel that spans a height of 4 LAB rows in MAX II devices. The vertical interconnect routes signals to and from LABs and I/O elements.