An Avalon interface (port) is a group of signals that are used collectively to implement a Qsys interface. Avalon Memory-Mapped (Avalon-MM) ports connect Avalon Memory-Mapped master ports and Avalon Memory-Mapped slave ports. An Avalon Memory-Mapped (Avalon-MM) master port initiates transactions in a Qsys system, and an Avalon Memory-Mapped (Avalon-MM) slave port is the collection of Avalon-MM signal types used to respond to transfer requests. Avalon Streaming (Avalon-ST) ports connect Avalon Streaming source ports and Avalon Streaming sink ports. Each port type includes a number of required signal types and can also include optional signal types, which are known as component specific signals. There are no naming requirements for the required signals; however, each signal must be assigned an Avalon signal type so that it is interpreted correctly by the Qsys software. If a signal is assigned the name of a signal type, it is assumed to be of that type.
Avalon ports do not connect together directly. Instead, Avalon ports connect to system interconnect, which translates signals between master and slave ports or source and sink ports. The system interconnect for Avalon-MM and Avalon-ST interfaces is quite different. For Avalon-ST interfaces, the interconnect creates a point-to-point connection between a source-sink pair. The interconnect for streaming interfaces is automatically optimized for the unidirectional flow of high-speed data.
For Avalon-MM interfaces, the system interconnect can be optimized to meet system requirements. Depending upon design requirements, adapters can be used to make trade-offs between size and performance, bandwidth and latency, or concurrency and resource use. For example, seldom accessed and low bandwidth components can be positioned on the far side of an adapter, where accesses to those components incurs a higher latency, and multiple masters must contend for those components as a group. Using an adapter results in a system with lower resource usage and higher overall frequency because there are fewer destinations to arbitrate for and lower supported concurrency.
Both Avalon-MM and Avalon-ST interfaces can optionally use backpressure to stall a data transfer. An Avalon-MM slave port asserts its waitrequest signal to indicate that it cannot accept data. Wait-states extend the read transfer and give a slave port one or more clock cycles to capture address and/or return valid readdata. Wait-states also decrease the throughput to a slave port. For example, a sustained sequence of transfers with zero wait-states can achieve a maximum of one transfer per clock cycle. With one wait-state, the maximum throughput is one transfer per two clock cycles.
If an Avalon-ST interface supports backpressure, the Avalon-ST sink port de-asserts ready to indicate that it cannot accept data. A READY_LATENCY parameter indicates the number of cycles from the time that ready is asserted until valid data can be written.