Avalon Memory-Mapped Interface Definition

The Avalon Memory-Mapped (Avalon-MM) interface is an interface protocol for use in connecting master and slave components in an Qys system. The protocol connects address-based read/write interfaces typical of an Avalon memory-mapped master that usually controls a number of Avalon memory-mapped slave peripherals. The typical Avalon-MM master is a microprocessor; typical slaves include: memories, UARTs and timers. In contrast to the Avalon-MM interface, the Avalon Streaming (Avalon-ST) interface protocol is used for very high-bandwidth, unidirectional traffic connecting source-sink pairs.

The Avalon-MM interface defines:

• A set of signal types
• The behavior of these signals
• The types of transfers supported by these signals

For example, you can use the Avalon-MM interface to describe a traditional peripheral interface, such as SRAM, that supports only simple, fixed-cycle read/write transfers. On the other hand, the Avalon-MM interface can also be used to describe a more complex pipelined interface capable of burst transfers.

Some of the prominent features of the Avalon-MM interface are:

• Separate Address, Data and Control Lines—Provides the simplest interface to on-chip logic. By using dedicated address and data paths, Avalon-MM peripherals do not need to decode data and address cycles.
• Up to 1024-bit Data Width—Supports even-power-of-two data paths, up to 1024 bits.
• Synchronous Operation—Provides an interface optimized for synchronous, on-chip peripherals. Synchronous operation simplifies the timing behavior of the Avalon-MM interface, and facilitates integration with high-speed peripherals.
• Dynamic Bus Sizing—Handles the details of transferring data between peripherals with different data widths. Avalon-MM peripherals with differing data widths can interface easily with no special design considerations.
• Simplicity—Provides an easy-to-understand interface protocol with a short learning curve.
• Low resource Utilization—Provides an interface architecture that conserves on-chip logic resources.
• High performance—Provides performance up to one-transfer-per-clock.