TFFE Primitive
Parent topic: TFFE Primitive

Verilog HDL Example Instantiation


TFFE <instance_name> (.t(<input_wire>), .clk(<input_wire>),

   .clrn(<input_wire>), .prn(<input_wire>), .ena(<input_wire>),

   .q(<output_wire>));
Parent topic: TFFE Primitive

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