SRFF Primitive
Parent topic: SRFF Primitive

Verilog HDL Example Instantiation

SRFF <instance_name> (.s(<input_wire>), .r(<input_wire>),

   .clk(<input_wire>), .clrn(<input_wire>), .prn(<input_wire>),

   .q(<output_wire>));
Parent topic: SRFF Primitive

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