LUT_INPUT Primitive
Parent topic: LUT_INPUT Primitive

Verilog HDL Example Instantiation

LUT_INPUT <instance name> (.in(<input_wire>), .out(<output_wire>));

Parent topic: LUT_INPUT Primitive

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.