LCELL Primitive |
The following VHDL component declaration is located in theVHDL Design File (.vhd) DefinitionALTERA_MF_COMPONENTS.VHDin the<Quartus® Prime Standard Edition installation directory>\libraries\vhdl\alteradirectory.
component lcell port ( a_in : in std_logic; a_out : out std_logic); end component;