DLATCH Primitive
Parent topic: DLATCH Primitive

VHDL Component Declaration

COMPONENT DLATCH

   PORT (d   : IN STD_LOGIC;

        ena  : IN STD_LOGIC;

        clrn : IN STD_LOGIC;

        prn  : IN STD_LOGIC;

        q    : OUT STD_LOGIC);

END COMPONENT;
Parent topic: DLATCH Primitive

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