DFFE Primitive
Parent topic: DFFE Primitive

Verilog HDL Example Instantiation

DFFE <instance_name> (.d(<input_wire>), .clk(<input_wire>),

   .clrn(<input_wire>), .prn(<input_wire>), .ena(<input_wire>),

   .q(<output_wire>));
Parent topic: DFFE Primitive

Contact Altera | Legal Notice

Copyright© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS, STRATIX, and all other brands, unless noted otherwise, and/or trademarks of Altera Corporation in the U.S. and other countries.