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MARGIN_EXT_CAP_HDR_REG
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0x0 |
DisplayName: Margining Extended Capability Header.
Register Size: 32
Value After Reset: 0x1e010027
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This register provides capbility ID, capability version and next offset value for Margining Extended Capability. |
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MARGIN_PORT_CAPABILITIES_STATUS_REG
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0x4 |
DisplayName: Margining Port Capabilities and Status Register.
Register Size: 32
Value After Reset: 0x0
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This register indicates the status of the Margining feature. |
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MARGIN_LANE_CNTRL_STATUS0_REG
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0x8 |
DisplayName: Margining Lane Control and Status Register for Lane 0.
Register Size: 32
Value After Reset: 0x9c38
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The Margining Lane Control Register consists of control fields required for per-Lane margining.
The number of entries in this register are sized by Maximum Link Width. |
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MARGIN_LANE_CNTRL_STATUS1_REG
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0xc |
DisplayName: Margining Lane Control and Status Register for Lane 1.
Register Size: 32
Value After Reset: 0x9c38
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The Margining Lane Control Register consists of control fields required for per-Lane margining.
The number of entries in this register are sized by Maximum Link Width. |
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MARGIN_LANE_CNTRL_STATUS2_REG
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0x10 |
DisplayName: Margining Lane Control and Status Register for Lane 2.
Register Size: 32
Value After Reset: 0x9c38
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The Margining Lane Control Register consists of control fields required for per-Lane margining.
The number of entries in this register are sized by Maximum Link Width. |
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MARGIN_LANE_CNTRL_STATUS3_REG
|
0x14 |
DisplayName: Margining Lane Control and Status Register for Lane 3.
Register Size: 32
Value After Reset: 0x9c38
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The Margining Lane Control Register consists of control fields required for per-Lane margining.
The number of entries in this register are sized by Maximum Link Width. |