gmacgrp_mac_address0_high 

          Register 16 (MAC Address0 High Register)   

The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register. For example, if 0x112233445566 is received (0x11 in lane 0 of the first column) on the (G)MII as the destination address, then the MacAddress0 Register [47:0] is compared with 0x665544332211.

If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the MAC Address0 Low Register are written. For proper synchronization updates, the consecutive writes to this Address Low Register should be performed after at least four clock cycles in the destination clock domain.
Module Instance Base Address Register Address
i_emac_emac0 0xFF800000 0xFF800040
i_emac_emac1 0xFF802000 0xFF802040
i_emac_emac2 0xFF804000 0xFF804040

Size: 32

Offset: 0x40

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

ae

RO 0x1

reserved_30_16

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

addrhi

RW 0xFFFF

gmacgrp_mac_address0_high Fields

Bit Name Description Access Reset
31 ae 
Address Enable

This bit is always set to 1.
 RO 0x1
30:16 reserved_30_16 
Reserved
 RO 0x0
15:0 addrhi 
MAC Address0 [47:32]

This field contains the upper 16 bits (47:32) of the first 6-byte MAC address. The MAC uses this field for filtering the received frames and inserting the MAC address in the Transmit Flow Control (PAUSE) Frames.
 RW 0xFFFF