cpr 

         Component Parameter Register
Module Instance Base Address Register Address
i_uart_0_uart_address_block 0xFFC02000 0xFFC020F4
i_uart_1_uart_address_block 0xFFC02100 0xFFC021F4

Size: 32

Offset: 0xF4

Access: RO

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

rsvd_cpr_31to24

RO 0x0

fifo_mode

RO 0x8

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

rsvd_cpr_15to14

RO 0x0

dma_extra

RO 0x1

uart_add_encoded_param

RO 0x1

shadow

RO 0x1

fifo_stat

RO 0x1

fifo_access

RO 0x1

additional_feat

RO 0x1

sir_lp_mode

RO 0x0

sir_mode

RO 0x0

thre_mode

RO 0x1

afce_mode

RO 0x1

rsvd_cpr_3to2

RO 0x0

apbdatawidth

RO 0x2

cpr Fields

Bit Name Description Access Reset
31:24 rsvd_cpr_31to24 
Reserved bits [31:24] - Read Only
 RO 0x0
23:16 fifo_mode 
Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf
0x00 = 0,
0x01 = 16,
0x02 = 32,
toset
0x80 = 2048,
0x81- 0xff = reserved
Value Description
128 FIFO Depth 128 bytes
RO 0x8
15:14 rsvd_cpr_15to14 
Reserved bits [15:14] - Read Only
 RO 0x0
13 dma_extra 
Encoding of DMA_EXTRA configuration parameter value.
0 = FALSE,DW_apb_uart.ralf
1 = TRUE
Value Description
1 DMA Extra Supported
RO 0x1
12 uart_add_encoded_param 
Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 ID register present
RO 0x1
11 shadow 
Encoding of SHADOW configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 Shadow Supported
RO 0x1
10 fifo_stat 
Encoding of FIFO_STAT configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 FIFO Stat Supported
RO 0x1
9 fifo_access 
Encoding of FIFO_ACCESS configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 FIFO Access Supported
RO 0x1
8 additional_feat 
Encoding of ADDITIONAL_FEATURES configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 Additional Features Supported
RO 0x1
7 sir_lp_mode 
Encoding of SIR_LP_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0 LP Sir Mode Not Supported
RO 0x0
6 sir_mode 
Encoding of SIR_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
0 Sir Mode Not Supported
RO 0x0
5 thre_mode 
Encoding of THRE_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 Programmable Tx Hold Reg. Empty interrupt present
RO 0x1
4 afce_mode 
Encoding of AFCE_MODE configuration parameter value.
0 = FALSE,
1 = TRUE
Value Description
1 Auto Flow
RO 0x1
3:2 rsvd_cpr_3to2 
Reserved bits [3:2] - Read Only
 RO 0x0
1:0 apbdatawidth 
Encoding of APB_DATA_WIDTH configuration parameter value.
00 = 8 bits,
01 = 16 bits,
10 = 32 bits,
11 = reserved
Value Description
2 APB Data Width = 32-bits
RO 0x2