reg_memclockgating0

Module Instance	Base Address	Register Address
`iohmc_ctrl_inst_0_iohmc_ctrl_mmr_top_inst`	`0xF8010000`	`0xF8010138`

Size: 32

Offset: 0x138

Access: RW

Important: The value of a reserved bit must be maintained in software. When you modify registers containing reserved bit fields, you must use a read-modify-write operation to preserve state and prevent indeterminate system behavior.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`								`cfg_memclkgate_setting` `RW 0x0`

reg_memclockgating0 Fields

Bit	Name	Description	Access	Reset
7:0	`cfg_memclkgate_setting`	iohmc_ctrl_mmr_top_inst.cfg_memclkgate_setting Name:Memory Clock Control Setting Description:Set memory clocks behavior for Hard Memory Controller Each 2-bit field controls a specific memory clock pair. [7:6] – memory clock pair #3 [5:4] – memory clock pair #2 [3:2] – memory clock pair #1 [1:0] – memory clock pair #0 Memory clock behavior is controlled as follows: 2’b11 – Reserved 2’b10 – clock always enabled 2’b11 – clock disabled in low power states 2’b00 – clock always disabled	`RW`	`0x0`

Bit

Name

Description

Access

Reset

7:0

cfg_memclkgate_setting

iohmc_ctrl_mmr_top_inst.cfg_memclkgate_setting
Name:Memory Clock Control Setting
Description:Set memory clocks behavior for Hard Memory Controller
Each 2-bit field controls a specific memory clock pair.
[7:6] – memory clock pair #3
[5:4] – memory clock pair #2
[3:2] – memory clock pair #1
[1:0] – memory clock pair #0
Memory clock behavior is controlled as follows:
2’b11 – Reserved
2’b10 – clock always enabled
2’b11 – clock disabled in low power states
2’b00 – clock always disabled

RW

0x0